As the dimensions of integrated circuits decrease, lithographic constraints are tending toward the gates of field effect transistors (FETs) to be orientated in a single direction on a fixed pitch. This adds to an increase in the density of the wiring at the next level used to interconnect gates of two or more FETs which are also constrained by lithography. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.